Advance Conference Program

Sunday - July 4th 2010


Registration: 18:00 – 20:00


Monday - July 5th 2010

Opening Remark: 8:30 – 08:55


Invited talk: 9:00 –09:55

Prof. Dimitrios Soudris, National Technical University of Athens, Greece
European ICT Research: 2011-2012 Outlook for Components and Systems
Dr Panagiotis Tsarchopoulos, Project Officer, Computing Systems European Commission, DG INFSO/G3, Information and Communication Technologies - Embedded Systems & Control


Session M1A: 10:00 – 11:40
VLSI Design Issues

Jiang Xu Hong Kong University of Science and Technology, China

  1. SUT-RNS Forward and Reverse Converters
    Evangelos Vassalos, Dimitris Bakalis and Haridimos Vergos

  2. Clock Tree Synthesis with XOR Gates for Polarity Assignment
    Jianchao Lu and Baris Taskin

  3. A Fast Heuristic for Extending Standard Cell Libraries with Regular Macro Cells
    Christian Pilato, Fabrizio Ferrandi and Davide Pandini

  4. A BDD-based Design of an Area-Power Efficient Asynchronous Adder
    Gopal Paul, Rohit Reddy, C. R. Mandal and Bhargab B. Bhattacharya

  5. Efficient hardware looping units for FPGAs
    Nikolaos Kavvadias and Konstantinos Masselos


Session: M1B: 10:00 – 11:40
Embedded System Design

Dr Michael Huebner, KIT -Karlsruhe Institute of Technology, Germany

  1. Input-Output Selection Based Router for Networks-on-Chip
    Masoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila and Hannu Tenhunen
  2. Automatic Generation of Massively Parallel Hardware from Control-Intensive Sequential Programs
    Michael Dossis

  3. Efficient High Level Synthesis Exploration Methodology Combining Exhaustive and Gradient-Based Pruned Searching
    Sotirios Xydis, Christos Skouroumounis, Kiamal Pekmestzi, Dimitrios Soudris and George Economakos

  4. Adaptive Task Migration Policies for Thermal control in MPSoCs
    David Cuesta, Jose Luis Ayala, Jse Ignacio Hidalgo, David Atienza, Andrea Acquaviva and Enrico Macii

  5. A Scalable Bandwidth Aware Architecture for Connected Component Labeling
    Vikram Sampath Kumar, Kevin Irick, Ahmed Al Maashri and Vijaykrishnan Narayanan


Coffee Break: 11:45 – 12:10


Session M1A: 12:15 – 13:35
VLSI Design Issues

Prof. Chrysovalantis Kavousianos, University of Ioannina, Greece

  1. Exploration of 2D Cellular Automata as Binary Sequence Generators
    Athanasios Kakarountas, Efthymia Arvaniti and Ilias Mavridis

  2. Fine-grained fault tolerance for process variation-aware caches
    Tayyeb Mahmood and Soontae Kim

  3. Hierarchical DFT with Combinational Scan Compression, Partition Chain and RPCT
    Prakash Srinivasan and Ronan Farrell

  4. Master-Slave TMR Inspired Technique for Fault Tolerance of SRAM-based FPGA
    Farid Lahrach, Abderrahim Doumar,Eric Chatelet, Abderrazek Abdaoui

Session: M1B: 12:15 – 13:35
Embedded System Design

Dr Michael Huebner, KIT -Karlsruhe Institute of Technology, Germany

  1. LE1: A parameterizable, shared-memory VLIW Chip-Multiprocessor with hardware PThreads support
    David Stevens and Vassilios Chouliaras

  2. A Post-Compiling Approach that Exploits Code Granularity in Scratchpads to Improve Energy Efficiency
    Daniel P. Volpato, Alexandre K. I. Mendonca, Luiz C. V. dos Santos and Jose Luis Guntzel

  3. Systematic Exploration of Energy-Efficient Application-Specific Network-on-Chip Architectures
    Iasonas Filippopoulos, Iraklis Anagnostopoulos, Alexandros Bartzas, Dimitrios Soudris and George Economakos


On site Lunch break: 13:45 – 14:40


Invited talk: 14:45 – 15:40

Prof. Syed Kamrul Islam, University of Tennessee, USA
Challenges and perspectives of computer architecture beyond CMOS
Christian Garmat, CEA List, France


Session M1A: 15:45 – 17:25
VLSI Design Issues

Theocharis Theocharides, University of Cyprus, Cyprus

  1. Self-Freeze Linear Decompressors for Low Power Testing
    Vasileios Tenentes and Chrysovalantis Kavousianos

  2. Logical Core Algorithm: Improving Global Placement
    Felipe Pinto, Lucas Cavalheiro, Marcelo Johann and Ricardo Reis

  3. Safety Aware Place and Route for On-Chip Redundancy in Safety Critical Applications
    Romuald Girardey, Michael Hubner and Jurgen Becker

  4.  Inter-Process Communication using Pipes in FPGA-based Adaptive Computing
    Ming Liu, Zhonghai Lu, Wolfgang Kuehn and Axel Jantsch

  5. Highly Efficient Transforms Module Solution for a H.264/SVC Encoder
    Ronaldo Husemann, Altamiro Susin, Valter Roesler and Jose Valdeni

Session: M2B: 15:45 – 17:25
Cryptographic Hardware Engineering

Prof. Nicolas Sklavos, Technological Educational Institute of Patra, Greece

  1. BLAKE Hash Functions Family on FPGA: From the Fastest to the Smallest
    Nicolas Sklavos and Paris Kitsos

  2. Differential Power Analysis of CAST-128
    Kean Hong Boey, Yingxi Lu, Maire O'Neill and Roger Woods

  3. QCA Systolic Matrix Multiplier
     Liang Lu, Weiqiang Liu, Maire O'Neill and Earl Swartzlander Jr.

  4. Hardware Module Design for Ensuring Trust
    Apostolos Fournaris


Coffee Break: 17:30 –17:55


Session: M2A: 18:00 – 20:00
Reconfigurable Systems

Vijaykrishnan Narayanan, Pennsylvania State University, USA

  1. Accelerating Numerical Linear Algebra Kernels on a Scalable Run Time Reconfigurable Platform
    Prasenjit Biswas, Pramod P Udupa, Rajdeep Mondal, Keshavan Varadarajan, Mythri Alle, S. K Nandy and Ranjani Narayan

  2. Task Dispersal Measurement in Dynamic Reconfigurable NoCs
    Mohammad Hosseinabady and Jose Nunez-Yanez

  3. Defect and Variation Issues on Design Mapping of Reconfigurable Nanoscale Crossbars
    Behnam Ghavami, Alireza Tajari, Mohsen Raji and Hossein Pedram

  4. ASIC Design of Adaptive Control Unit for Reconfigurable Analog-to-Digital Converter
    Zulhakimi Razak, Ahmet Erdogan and Tughrul Arslan

  5. A Calibration Circuit for Reconfigurable Smart ADC for Biomedical Signal Processing
    Salwa Mostafa, Syed Islam, Wenchao Qu and Mohamed Mahfouz

  6. Fast Sequential FPGA Startup based on partial and dynamic Reconfiguration
    Michael Huebner, Joachim Meyer, Juanjo Noguera, Rodney Steward and Jurgen Becker

Session M3B: 18:00 – 20:00
Physical design

Prof. Amar Mukherjee,  University of Central Florida, USA

  1. A Body Biasing Method For Charge Recovery Circuits: Improving The Energy Efficiency and DPA-Immunity
    Mehrdad Khatir and Alireza Ejlali
  2. Memory-less Pipeline Dynamic Circuit Design Technique
    Themistoklis Haniotakis, Zaher Owda and Yiorgos Tsiatouhas
  4. A Floating Gate MOSFET Based Current Reference with Subtraction Technique
    V. Sureshbabu, P.S. Haseena and M.R. Baiju

  5. A low power, high performance threshold logic-based standard cell multiplier in 65 nm CMOS
    Samuel Leshner, Krzysztof Berezowski, Xiaoyin Yao, Gayathri Chalivendra, Saurabh Patel and Sarma Vrudhula

  6. Pattern-Driven Clock Tree Routing with Via Minimization
    Ali Mohammadi Farhangi and Asim Al-Khalili

  7. Ultra-Low-Power Sensor Signal Monitoring and Impulse RadioArchitecture for Biomedical Applications
    Mohammad Haider, Ashraf Islam and Syed Islam


Opening Ceremony
(Meeting point: Conference Centre at 20:45)

Iakovateios Library

21:00 – 21:10 Conference Welcome
                          ISVLSI 2010 Organizing Committee

21:10 – 21:20
Welcome Salutation
                          Mr Dionysios Georgatos, Prefect of Kefalonia and Ithaca

21:20 – 21:30 Welcome Salutation
                          Mrs Nopi Alexandropoulou - Charitatou, Mayor of Lixouri

21:30 – 21:45 Kefalonia – The hidden Treasure of Greece
                          Mrs Evi Douka, Perfecture of Kefalonia and Ithaca

21:45 – 22:15 Traditional Kefalonian Dances & Cocktail
                          Dancing Group of Municipality of Paliki

Tuesday - July 6th 2010

Invited talk: 9:00 – 09:55

Prof. Chrysovalantis Kavousianos, University of Ioannina, Greece
Digital Microfluidic Biochips: A Vision for Functional Diversity and More than Moore
Professor Krishnendu Chakrabarty, Department of Electrical and Computer Engineering, Duke University


Session T1: 10:00 – 11:25
Research Project Workshop

Prof. Dimitrios Soudris, National Technical University of Athens, Greece
Prof. Nicolas Sklavos, Technological Educational Institute of  Patras, Greece

  1. MULTICUBE: Multi-Objective Design Space Exploration of Multi-Core Architectures
    Cristina Silvano, William Fornaciari, Gianluca Palermo, Vitttorio Zaccaria, Fabrizio Castro, Marcos Martinez, Sara Bocchio, Roberto Zafalon, Prabhat Avasare, Geert Vanmeerbeeck, Chantal Ykman-Couvreur, Maryse Wouters, Carlos Kavka, Luka Onesti, Alessandro Turco, Umberto Bondi, Giovanni Mariani, Hector Posadas, Eugenio Villar, Chris Wu, Fan Dongrui, Zhang Hao, Tang Shibin
  2. 2PARMA: Parallel Paradigms and Run-time Management Techniques for  Many-Core Architectures
    C. Silvano , W. Fornaciari , S. Crespi Reghizzi , G. Agosta , G. Palermo , V. Zaccaria , P. Bellasi , F. Castro , S. Corbetta , A. Di Biagio , E. Speziale, M. Tartara, D. Siorpaes, H. Hübert , B. Stabernack , J. Brandenburg, M. Palkovic, P. Raghavan , C. Ykman-Couvreur, A. Bartzas , S. Xydis , D. Soudris , T. Kempf , G. Ascheid, H. Meyr, J. Ansari, P. Mähönen, B. Vanthournout

  3. System Level Design for Embedded Reconfigurable Systems using MORPHEUS platform
    Paul Brelet, Arnaud Grasset, Philippe Bonnot, Frank Ieromnimon, Dimitrios Kritharidis and Nikolaos Voros


Coffee Break: 11:30 – 11:55


Invited talk: 12:00 – 12:25

Dr Nikolaos Moschopoulos, Sitel Semiconductor Hellas S.A., Greece

Innovating to address market opportunities & technology challenges: HSIA case studies
Dr. George Koutsoyannopoulos, Hellenic Semiconductors Industry Association, CEO of Helic Inc


Session T1: 12:30 – 13:55
Research Project Workshop (continued)

Prof. Dimitrios Soudris, National Technical University of Athens, Greece
Prof. Nicolas Sklavos, Technological Educational Institute of  Patras, Greece

  1. The SATURN Approach to SysML-based HW/SW Codesign
    Wolfgang Mueller, Da He, Fabian Mischkalla, Arthur Wegele, Paul Whiston, Nikolaos Mitas, Dimitrios Kritharidis, Pablo Peñil, Eugenio Villar, Florent Azcarate, Manuel Carballeda

  2. Mapping embedded applications on MPSoC – The MNEMEE approach
    Christos Baloukas, Lazaros Papadopoulos, Dimitrios Soudris, Sander Stuijk, Olivera Jovanovic, Florian Schmoll, Daniel Cordes, Robert Pyka, Arindam Mallik, Stylianos Mamagkakis, François Capman, Séverin Collet, Nikolaos Mitas, Dimitrios Kritharidis

  3. Mapping Optimisation for Scalable multi-core ARchiTecture: The MOSART approach
    Sylvain Aguirre, Michel Sarlotte, Bernard Candaele, Iraklis Anagnostopoulos, Sotirios Xydis, Alexandros Bartzas, Dimitris Bekiaris, Dimitrios Soudris, Zhonghai Lu, Xiaowen Chen, Sandro Penolazzi, Jean-Michel Chabloz, Axel Jantsch, Ahmed Hemani, Geert Vanmeerbeeck, Jari Kreku, Kari Tiensyrj, Nikolaos Mitas, Dimitrios Kritharidis, Andreas Wiefrink, Bart Vanthournout, Philippe Martin


On site Lunch break: 14:00 – 14:55


Invited talk: 15:00 – 15:55

Dr Michael Huebner, KIT -Karlsruhe Institute of Technology, Germany
Small worlds: the dynamics of NoCs in tomorrow SoC architecture
Marcello Coppola, R&D Director, STMicroelectronics


Coffee Break: 16:00 – 16:25


Session: T2A: 16:30 – 19:30
Poster Session

Dr Michael Huebner, KIT -Karlsruhe Institute of Technology, Germany

  1. P1: A Novel, Variable Resolution Flash ADC with Sub Flash Architecture 
    Mahesh Kumar A, Sreehari V, Moorthy Muthukrishnan N and Srinivas M.B

  2. P2: Bitstream Efficiency of Field Programmable One-Hot Arrays 
    Mark Arnold, Panagiotis Vouzis and Jung Cho

  3. P3: A Family of Area-Time Efficient Modulo $2^n+1$ Adders 
    Haridimos Vergos

  4. P4: A High-Level Mapping Algorithm Targeting 3D NoC Architectures with Multiple Vdd 
    Kostas Siozos, Iraklis Anagnostopoulos and Dimitrios Soudris

  5. P5: Towards supporting Fault-Tolerance in FPGAs 
    Kostas Siozios, Dimitrios Soudris and Dionisios Pnevmatikatos

  6. P6: Combining Unspecified Test Data Bit Filling Methods and Run Length Based Codes to Estimate Compression, Power and Area overhead 
    Usha Mehta, Kankar Dasgupta and Niranjan Devashrayee

  7. P7: A Novel On-Chip Interconnection Topology for Mesh-Connected Processor Arrays
    Xiaofang Wang

  8. P8: BBVC-3D-NoC: An Efficient 3D NoC Architecture Using Bidirectional Bisynchronous Vertical Channels 
    Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila and Hannu Tenhunen

  9. P9: Generation and Exploration of Layouts for Area-Efficient Barrel Shifters
    Alen Bardizbanyan, Kasyab P. Subramaniyan and Per Larsson-Edefors

  10. P10: A Reverse Converter for the Enhanced Moduli Set {2n–1, 2n+1, 22n, 22n+1–1} Using CRT and MRC
    Amir Sabbagh Molahosseini and Keivan Navi

  11. P11: Impact of Process Variations on Flip-Flops Energy and Timing Characteristics
    Marco Lanuzza, Pasquale Corsonello, Fabio Frustaci and Stefania Perri

  12. P12: Side Channel Attacks Cryptanalysis Against Block Ciphers Based on FPGA Devices
    Anestis Bechtsoudis and Nicolas Sklavos

  13. P13: Supporting Efficient Synchronization in Multi-core NoCs Using Dynamic Buffer Allocation Technique
    Xiaowen Chen, Zhonghai Lu, Axel Jantsch and Shuming Chen

  14. P14: Autonomous Design in VLSI: Growing and Learning on Silicon
    Ludovic Krundel, David Mulvaney and Vassilios Chouliaras

Session: T2B: 16:30 – 19:30
PhD Forum

Michael Huebner, KIT -Karlsruhe Institute of Technology, Germany

  1. PF1: High-Performance TSV Architecture for 3-D ICs
    Masoud Daneshtalab, Masoumeh Ebrahimi and Hannu Tenhunen

  2. PF2: Mixed-Signal Diverse Redundant System for Safety Critical Applications in FPGA
    Romuald Girardey, Michael Hübner and Jürgen Becker

  3. PF3: Design Automation and Analysis of Resonant Rotary Clocking Technology in Multi-GHz Range
    Vinayak Honkote

  4. PF4: System Level Design of Complex Hardware Applications using ImpulseC
    Georgia Kalogeridou, Nikolaos S. Voros and Konstantinos Masselos

  5. PF5: Two-dimensional dynamic multigrained reconfigurable hardware
    Lars Braun and Jürgen Becker

  6. PF6: FPGA-based Runtime Adaptive Multiprocessor Approach for Embedded High Performance Computing Applications
    Diana Goehringer and Juergen Becker

  7. PF7: Performance Analysis of 3D NoCs Partitioning Methods
    Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg and Hannu Tenhunen

  8. PF8: Autonomous Design in VLSI: an In-House Universal Cellular Neural Platform
    Ludovic Krundel, David Mulvaney and Vassilios Chouliaras
  9. PF9: High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures
    Sotirios Xydis, Kiamal Pekmestzi, Dimitrios Soudris and George Economakos


Official Conference Banquet
(Meeting point: Conference Centre at 20:45)

21:30 – 21:40 ISVLSI 2010 Best Paper Award
Conference Organizing Committee

21:40 – 21:50 ISVLSI 2010 Best PhD Forum Award
Conference Organizing Committee

22:00 –           Dinner with traditional Kefalonian music (Kantades)


Wednesday - July 7th 2010

Invited talk: 09:00 – 09:55

Prof. Nicolas Sklavos, Technological Educational Institute of Patra, Greece
Reconfigurable Architectures for Bioinformatics Applications
Professor Apostolos Dollas,
Department of Electronic and Computer Engineering, Technical University of Crete


Session W1A: 10:00 – 12:00
Advanced Mixed Signal Design

Prof. Syed Kamrul Islam, University of Tennessee, USA

  1. Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs
    Ankit More and Baris Taskin

  2. Testing Parametric and Catastrophic Faults in Mixed-Signal Integrated Circuits using Wavelets
    Alexios Spyronasios, Michael Dimopoulos, Nikolas Papadopoulos and Alkis Hatzopoulos

  3. A Receiver Circuit for Low-Swing Interconnect Schemes
    Yannis Moisiadis and Yiorgos Tsiatouhas

  4. An 8-bit Voltage Mode Analog to Digital Converter Based on Integer Division
    Nikos Petrellis, Michael Birbas, John Kikidis and Alexios Birbas

  5. DC Offset Modeling and Noise Minimization for Differential Amplifier In Subthreshold Operation
    Kapil Rajput, Anil Saini and SC Bose

  6. Fast Evaluation of Analog Circuits Using Linear Programming
    Zach Cashero, Allen Chen, Ryan Hoppal and Tom Chen

Session W1B: 10:00 – 12:00
Advanced High-Performance Design Techniques

Prof. Cristina Silvano, Politecnico di Milano, Italy

  1. Low Power Single Electron OR/NOR Gate Operating at 10 GHz
    Thomas Tsiolakis, George Alexiou and Nikos Konofaos

  2. Performance Optimization of Conventional MOS-like Carbon Nanotube-FETs based on Dual-gate-material
    Hailiang Zhou, Minxuan Zhang, Liang Fang and Yue Hao

  3. A Mesh-buffer Displacement Optimization Strategy
    Guilherme Flach, Gustavo Wilke, Marcelo Johann and Ricardo Reis

  4. BLAS Comparison on FPGA, CPU and GPU
    Srinidhi Kestur, John Davis and Oliver Williams

  5. Novel architecture for highly hardware efficient implementation of real time Matrix Inversion using Gauss Jordan technique
    Chandrakanth Vipparla and Ramachandra Kuloor


Coffee Break: 12:05 – 12:30


Session W1A: 12:35 – 13:35
Advanced Mixed Signal Design  (continued)

Prof. Vassileios Triantafyllou, Technological Educational Institute of  Mesolonghi, Greece
Prof. Spyros Louvros, Technological Educational Institute of Mesolonghi, Greece

  1. FGMOS based built-in current sensor for low supply voltage analog and mixed-signal circuits testing
    Stylianos Siskos

  2. A Sub-1ΞΌA Low-Power FSK Modulator for Biomedical Sensor Circuits
    Kai Zhu, Mohammad Haider, Song Yuan and Syed Islam

  3. Design of a Bandgap Reference Circuit with Trimming for Operation at Multiple Voltages and Tolerant to Radiation in 90nm CMOS Technology
    Eva Vilella and Angel Dieguez

Session W2B: 12:35 – 13:35
Design for Reliability

Dr. Nikolaos Moschopoulos, Sitel Semiconductor Hellas S.A. , Greece

  1. Reliability Analysis and Improvement in Nano Scale Design
    Mahtab Niknahad, Michael Huebner and Juergen Becker

  2. Reliability-Aware Dynamic Voltage and Frequency Scaling
    Farshad Firouzi, mostafa Salehi, Fan Wang and S. M. Fakhraie

  3. TRB: Tag Replication Buffer for Enhancing the Reliability of the Cache Tag Array
    Shuai Wang, Jie Hu and Sotirios G. Ziavras


On site Lunch break: 13:45 – 14:40


Session: W2A: 14:45 – 16:45
Architecture-Level Design Solutions


Marcello Coppola, R&D Director, STMicroelectronics

  1. A Delay Model of Two-Cycle NoC Router in 2D-Mesh Network
    QI Shubo, LI Jinwen, XING Zuocheng, JIA Xiaomin, ZHANG Minxuan

  2. Tree-Based Routing for Faulty On-Chip Networks with Mesh Topology
    Hsin-Chou Chi, Yu-Hong Jhang and Wen-Shu Chen
  3. A Hierarchical Hybrid Optical-Electronic Network-on-Chip
    Kwai Hung Mo, Yaoyao Ye, Xiaowen Wu, Wei Zhang, Weichen Liu and Jiang Xu

  4. A High Throughput Low Power FIFO used for GALS NoC Buffers Mohammad Fattah, Abdurrahman Manian, Abbas Rahimi and Siamak Mohammadi

  5. An Artificial Neural Network-Based Hotspot Prediction Mechanism for NoCs
    Elena Kakoulli, Vassos Soteriou and Theocharis Theocharides

  6. A Homogeneous MPSoC with Dynamic Yask Mapping for Software Defined Radio
    ECamille Jalier, Didier Lattard, Gilles Sassatelli, Pascal Benoit and Lionel Torres


Session W3B: 14:45 – 16:45
Emerging Devices for Memory Design and Nanocomputing

Prof. Dimitrios Soudris, National Technical University of Athens, Greece
Prof. Spyros Louvros, Technological Educational Institute of Mesolonghi, Greece

  1. Recovery Boosting: A Technique to Enhance NBTI Recovery in SRAM Arrays
    Taniya Siddiqua and Sudhanva Gurumurthi

  2. XMSIM: EXtensible Memory SIMulator for Early Memory Hierarchy Evaluation
    Theodoros Lioris, Grigoris Dimitroulakos and Kostas Masselos

  3. Modeling and Simulation of Multi-Operation Microcode-based Built-In Self Test for Memory Fault Detection and Repair
    R.K. Sharma and Aditi Sood

  4. A novel 1.8V, 1066Mbps, DDR2, DFI-compatible, Memory Interface
    Alexis Alexandropoulos, Efthimios Davrazos, Fotis Plessas and Michael Birbas

  5. A New Low-Power Soft-Error Tolerant SRAM Cell
    Nicholas Axelos, Kiamal Pekmestzi and Nikolaos Moschopoulos

  6. The impact of process faults on specific parameters of a 1.9GHz CMOS mixer
    Anastasios Karagounis, Basilis Kotsos, Nikolaos Assimakis, Athanasios Polyzos and  Eyrikleia Petropoulou


Coffee Break: 16:50 – 17:15


Session: W2A: 17:20 – 18:40
Architecture-Level Design Solutions (continued)

Prof. Konstantinos Goutis, University of Patras, Greece

  1. Stochastic Automata Network Based Approach for Performance Evaluation of Network-on-Chip Communication Architecture
    Ulhas Deshmukh and Vineet Sahula

  2. Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model
    Naoya Onizawa, Tomoyoshi Funazaki, Atsushi Matsumoto and Takahiro Hanyu

  3. An Analytical Framework with Bounded Deflection Adaptive Routing for Networks-on-Chip
    Pavel Ghosh, Arvind Ravi and Arunabha Sen

  4. Hybrid QoS method for Networks-on-Chip
    Shijun Lin, Jianghong Shi and Huihuang Chen

  5. A Scalable Bandwidth Aware Architecture for Connected Component Labeling
    Vikram Sampath Kumar, Kevin Irick, Ahmed Al Maashri and Vijaykrishnan Narayanan


Session W3C: 17:20 – 18:40
Novel System Design Trends with Emerging Technologies

Prof. Dimitrios Soudris, National Technical University of Athens, Greece

  1. Improved Yield in Nanotechnology Circuits using Non-square Meshes
    Nikolaos Mavrogiannakis, Costas Argyrides and Dhiraj Pradhan

  2. Dynamic Power Management on LDPC Decoders
    Erick Amador, Raymond Knopp, Vincent Rezard and Renaud Pacalet

  3. Implementation Analysis of a Dynamic Energy Management Approach Inspired by Game-Theory
    Imen mansouri, Camille jalier, Fabien Clermidy, Pascal Benoit and Lionel Torres

  4. Data-flow Driven Equivalence Checking for Verification of Code Motion Techniques
    Chandan Karfa, Dipankar Sarkar and Chittaranjan Mandal


Closing Session: 19:00 – 19.30


Organized by
TESYD TESYD Embedded Lab IEEE GOLD Nomarxia Paliki